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SyncMOS Technologies Inc.
January 2003
Preliminary
SM79108
8 - Bit Micro-controller
with 8KB flash & 256 Bytes RAM embedded
Product List
SM79108L25, 25 MHz 8KB internal memory MCU SM79108C40, 40 MHz 8KB internal memory MCU
Features
Working voltage: 3.0V ~ 3.6V For L Version 4.5V ~ 5.5V For C Version General 8052 family compatible 12 clocks per machine cycle 8 KB internal flash memory 256 bytes on-chip data RAM Three 16 bit timers/counters Four 8-bit I/O ports for PDIP package Four 8-bit I/O ports + one 4-bit I/O ports for PLCC or QFP package A14 x 4 LCD driver (P0, P2, ALE, PSEN) 1 Channel SPWM (P1.2) 1 Channel PWM (P1.5) Full duplex serial channel Bit operation instruction Industrail Level 8-bit unsigned division 8-bit unsigned multiply BCD arithmetic Direct addressing Indirect addressing Nested interrupt Two priority level interrupt A serial I/O port Power save modes: Idle mode and power down mode Code protection function One watch dog timer (WDT) Low EMI (inhibit ALE)
Description
The SM79108 series product is an 8 - bit single chip micro controller with 8 KB flash & 256 bytes RAM embedded. It has 4-channel, 8-bit ADC function build-in, 1-channel SPWM and 1-channel PWM build-in and A14(segment) x 4(common) LCD driver. It provides hardware features and a powerful instruction set necessary to make it a versatile and cost effective controller for those applications demand up to 32 I/O pins for PDIP package or up to 36 I/O pins for PLCC/QFP package, or applications which need up to 64K byte flash memory for program and/or for data. To program the flash block, a commercial programmer is capable to do it.
Ordering Information
yywwv: production date code identifier SM79108ihhk yy: year, ww: weak, v: version i: process identifier {L=3.0V ~ 3.6V, C=4.5V ~ 5.5V} hh: working clock in MHz {25, 40} k: package type postfix {as below table}
Pin/Pad Configuration page 2 page 2 page 2
Postfix P J Q
Package 40L PDIP 44L PLCC 44L QFP
Dimension page 22 page 23 page 24
Taiwan 4F, No. 1 Creation Road 1, Science-based Industrial Park, Hsinchu, Taiwan 30077 TEL: 886-3-578-3344 #2667 886-3-579-2987 FAX: 886-3-5792960 886-3-5780493
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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January 2003
Preliminary
SM79108
Pin Configurations
P0.4/AD4/SEG9 P0.5/AD5/SEG8 P0.6/AD6/SEG7 P0.7/AD7/SEG6 #EA P2.7/A15/SEG3
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VDD P0.0/AD0/SEG13 P0.1/AD1/SEG12 P0.2/AD2/SEG11 P0.3/AD3/SEG10 P0.4/AD4/SEG9 P0.5/AD5/SEG8 P0.6/AD6/SEG7 P0.7/AD7/SEG6 #EA ALE/SEG5 #PSEN/SEG4 P2.7/A15/SEG3 P2.6/A14/SEG2 P2.5/A13/SEG1 P2.4/A12/SEG0 P2.3/A11/COM3 P2.2/A10/COM2 P2.1/A9/COM1 P2.0/A8/COM0 SEG10/AD3/P0.3 SEG11/AD3/P0.2 SEG12/AD3/P0.1 SEG13/AD3/P0.0 VDD P4.2 T2/P1.0 T2EX/P1.1 SPWM/P1.2 P1.3 P1.4
T2EX/P1.1 SPWM/P1.2 P1.3 P1.4 PWM/P1.5 P1.6 P1.7 RES RXD/P3.0 TXD/P3.1 #INT/P3.2 #INT1/P3.3 ADC0/T0/P3.4 ADC1/T1/P3.5 ADC2/#WR/P3.6 ADC3/#RD/P3.7 XTAL2 XTAL1 VSS
2 3 4 5 6 7
34 35 36 37 38 39 40 41 42 43 44
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11
P4.1 ALE/SEG5
T2/P1.0
1
P2.6/A14/SEG2 P2.5/A13/SEG1
#PSEN/SEG4
P2.4/A12/SEG0 P2.3/A11/COM3 P2.2A10/COM2 P2.1/A9/COM1 P2.0A8/COM0 P4.0 VSS XTAL1 XTAL2 P3.7/#RD/ADC3 P3.6/#WR/ADC2
8 9 10 11
SM79108 jhhQ 44L QFP (Top View)
SM79108 ihhP 40L PDIP (Top View)
P1.3 P1.2/SPWM
5
12
13 14 15 16 17 18 19 20
PWM/P1.5 P1.6
P1.7 RES RXD/P3.0
TXD/P3.1
#INT1/P3.3 ADC0/T0/P3.4
#INT0/P3.2
P1.1/T2EX P1.0/T2 P4.2 VDD P0.0/AD0/SEG13 P0.1/AD1/SEG12
P1.4
6
4
3
2
1 44 43 42 41 40
P0.2/AD2/SEG11
P0.3/AD3/SEG10
PWM/P1.5 P1.6 P1.7 RES RXD/P3.0 P4.3 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 ADC0/T0/P3.4 ADC1/T1/P3.5
7 8 9 10 11 12 13
39 38 37
P0.4/AD4/SEG9 P0.5/AD5/SEG8 P0.6/AD6/SEG7 P0.7/AD7/SEG6 #EA P4.1 ALE/SEG5 #PSEN/SEG4 P2.7/A15/SEG3 P2.6/A14/SEG2 P2.5/A13/SEG1
SM79108 jhhJ 44L PLCC
(Top View)
36 35 34 33 32 31 30 29
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
ADC2/#WR/P3.6 ADC3/#RD/P3.7
XTAL2 XTAL1 VSS
P4.0
COM2/A10/P2.2
Specifications subject to change without notice,contact your sales representatives for the most recent information.
COM3/A11/P2.3
SEG0/A12/P2.4
COM0/A8/P2.0
COM1/A9/P2.1
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P4.3
SM79108 01/03
SyncMOS Technologies Inc.
January 2003 Block Diagram
Stack Pointer
Preliminary
SM79108
Timer 2
Timer 1
Timer 0
Decoder & Register
256 bytes RAM
WDT
RES Reset Circuit to pertinent blocks Acc to whole chip Buffer2 Buffer1
Buffer
DPTR
Vdd Vss Power Circuit
PC Incrementer
Interrupt Circuit
to pertinent blocks
ALU
Program Counter
XTAL2 XTAL1 #EA ALE/SEG5 #PSENSEG4 Timing Generator to whole system
PSW
Register
Instruction Register
8K bytes ADC Port 0 Latch SPWM PWM LCD Driver (14 x 4) Port 1 Latch Port 2 Latch Port 3 Latch Flash Memory
Port 0 Driver & Mux 8
Port 1 Port 2 Port 3 Driver & Mux Driver & Mux Driver & Mux 8 8 8
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SyncMOS Technologies Inc.
January 2003 Pin Descriptions
40L 44L 44L PDIP QFP PLCC Symbol Pin# Pin# Pin# 1 40 2 P1.0/T2 2 41 3 P1.1/T2EX 3 42 4 P1.2/SPWM 4 43 5 P1.3 5 44 6 P1.4 6 1 7 P1.5/PWM 7 2 8 P1.6 8 3 9 P1.7 9 4 10 RES 10 5 11 P3.0/RXD 11 7 13 P3.1/TXD 12 8 14 P3.2/#INT0 13 9 15 P3.3/#INT1 14 10 16 P3.4/T0/ADC0 15 11 17 P3.5/T1/ADC1 16 12 18 P3.6/#WR/ADC2 17 13 19 P3.7/#RD/ADC3 18 14 20 XTAL2 19 15 21 XTAL1 20 16 22 VSS 21 18 24 P2.0/A8/COM0 22 19 25 P2.1/A9/COM1 23 20 26 P2.2/A10/COM2 24 21 27 P2.3/A11/COM3 25 22 28 P2.4/A12/SEG0 26 23 29 P2.5/SEG1 27 24 30 P2.6/SEG2 28 25 31 P2.7/SEG3 29 26 32 #PSEN/SEG4 30 27 33 ALE/SEG5 31 29 35 #EA 32 30 36 P0.7/AD7/SEG6 33 31 37 P0.6/AD6/SEG7 34 32 38 P0.5/AD5/SEG8 35 33 39 P0.4/AD4/SEG9 36 34 40 P0.3/AD3/SEG10 37 35 41 P0.2/AD2/SEG11 38 36 42 P0.1/AD1/SEG12 39 37 43 P0.0/AD0/SEG13 40 38 44 VDD 17 23 P4.0 28 34 P4.1 39 1 P4.2 6 12 P4.3 Active I/O (GPIO) i/o i/o i/o i/o i/o i/o i/o i/o i i/o i/o i/o i/o i/o i/o i/o i/o o i i/o i/o i/o i/o i/o i/o i/o i/o o o i i/o i/o i/o i/o i/o i/o i/o i/o i i/o i/o i/o i/o Names
Preliminary
SM79108
H
-/L -/L
L
bit 0 of port 1 & timer 2 clock out bit 1 of port 1 & timer 2 control bit 2 of port 1 & SPWM channel bit 3 of port 1 bit 4 of port 1 bit 5 of port 1 & PWM channel bit 6 of port 1 bit 7 of port 1 Reset bit 0 of port 3 & receive data bit 1 of port 3 & transmit data bit 2 of port 3 & low true interrupt 0 bit 3 of port 3 & low true interrupt 1 bit 4 of port 3 & ADC channel 0 & Timer 0 bit 5 of port 3 & ADC channel 1 &Timer 1 bit 6 of port 3 & ADC channel 2 & external memory write bit 7 of port 3 & ADC channel 3 & external memory read Crystal out Crystal in Sink Voltage, Ground bit 0 of port 2 & bit 8 of external memory address & LCCD common 0 output bit 1 of port 2 & bit 9 of external memory address & LCCD common 1 output bit 2 of port 2 & bit 10 of external memory address & LCCD common 2 output bit 3 of port 2 & bit 11 of external memory address & LCCD common 3 output bit 4 of port 2 & bit 12 of external memory address & LCCD seg 0 output bit 5 of port 2 & LCCD seg 1 output bit 6 of port 2 & LCCD seg 2 output bit 7 of port 2 & LCCD seg 3 output program storage enable & LCCD seg 4 output address latch enable & LCCD seg 5 output external access bit 7 of port 0 & data/address bit 7 of external memory & LCCD seg 6 output bit 6 of port 0 & data/address bit 6 of external memory & LCCD seg7 output bit 5 of port 0 & data/address bit 5 of external memory & LCCD seg 8 output bit 4 of port 0 & data/address bit 4 of external memory & LCCD seg 9 output bit 3 of port 0 & data/address bit 3 of external memory & LCCD seg 10 output bit 2 of port 0 & data/address bit 2 of external memory & LCCD seg 11 output bit 1 of port 0 & data/address bit 1 of external memory & LCCD seg 12 output bit 0 of port 0 & data/address bit 0 of external memory & LCCD seg 13 output Drive Voltage, Vcc bit 0 of Port 4 bit 1 of Port 4 bit 2 of Port 4 bit 3 of Port 4
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SFR Memory MAP
SyncMOS Technologies Inc.
January 2003
Preliminary
SM79108
SFR Memory MAP
0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H 0C0H 0B8H 0B0H 0A8H 0A0H 98H 90H 88H 80H
B ACC P4 PSW T2CON IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TL1 DPH TH0 (Reserved) TH1 ADSCR SBUF P0CON IE1 IFR SPWMC P1CON SPWMD0 P2CON P3CON WDTC WDTKEY ADCD PCON T2MOD IP1 PWMD0 RCAP2L PWMC0 RCAP2H TL2 TH2 SCONF LCDB0 LCDB1 LCDB2 LCDB3 LCDB4 LCDB5 LCDB6 LCDCON
0FFH 0F7H 0EFH 0E7H 0DFH 0D7H 0CFH 0C7H 0BFH 0B7H 0AFH 0A7H 9FH 97H 8FH 87H
Note: The text of SFRs with bold type characters are Extension Special Function Registers for SM79108
Addr 8EH 8FH 97H 9AH 9BH 9CH 9DH 9FH 0A3H 0A4H 0A9H 0AAH 0B3H 0B9H 0BFH 0D3H 0D8H 0DFH 0E1H SFR ADSCR ADCD WDTKEY P0CON P1CON P2CON P3CON WDTC SPWMD0 IE1 IFR PWMD0 IP1 SCONF PWMC0 P4 LCDB0 Reset 0000_00** 00H 00H 00H **0*_*0** 00H 00H 000*_*000 00H ****_0*** ****_0*** 00H ****_0*** 0***_***0 ****_*000 ****_1111 Lout_en SEG0 Lcd_en SEG0 SEG SEG0 SEG0 SEG1 00H P4.3 WDR PWMD07 PWMD06 PWMD05 PWMD04 SEG3 ADCE3 WDTE SEG2 ADCE2 R 7 COM AD7 SEG6 6 CON AD6 SEG7 5 ADCSS1 AD5 SEG8 PWME0 SEG1 ADCE1 CLEAR SEG0 ADCE0 PS2 BRM02 PS1 SPFS1 SPWMD04 SPWMD03 SPWMD02 SPWMD01 SPWMD00 EADC ADCIF PWMD03 PADC Reserved PBS P4.2 LS2 SEG1 PFS1 P4.1 LS1 SEG1 ALEI PFS0 P4.1 LS0 SEG1 PWMD02 PWMD01 PWMD00 BRM01 PS0 SPFS0 BRM00 COME3 4 ADCSS0 AD4 SEG9 3 CH1 AD3 SEG10 2 CH0 AD2 SEG11 SPWME0 COME2 COME1 COME0 1 Reserved AD1 SGE12 0 Reserved AD0 SEG13
WDTKEY7 WDTKEY6 WDTKEY5 WDTKEY4 WDTKEY3 WDTKEY2 WDTKEY1 WDTKEY0
SPWMC0 ****_**00
LCDCON 000*_*000
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January 2003
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SM79108
Addr 0E2H 0E3H 0E4H 0E5H 0E6H 0E7H
SFR LCDB1 LCDB2 LCDB3 LCDB4 LCDB5 LCDB6
Reset 00H 00H 00H 00H 00H 00H
7 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12
6 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12
5 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12
4 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12
3 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13
2 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13
1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13
0 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13
1. Watch Dog Timer
The Watch Dog Timer (WDT) is a 16-bit free-running counter that generate reset signal if the counter overflows. The WDT is useful for systems which are susceptible to noise, power glitches, or electronics discharge which causing software dead loop or runaway. The WDT function can help user software recover from abnormal software condition. The WDT is different from Timer0, Timer1 and Timer2 of general 8052. To prevent a WDT reset can be done by software periodically clearing the WDT counter. User should check WDR bit of SCONF register whenever unpracticed reset happened The purpose of the secure procedure is to prevent the WDTC value from being changed when system runaway. There is a 250KHz RC oscillator embedded in chip. Set WDTE = "1" will enable the RC oscillator and the frequency is independent to the system frequency. To enable the WDT is done by setting 1 to the bit 7 (WDTE) of WDTC. After WDTE set to 1, the 16-bit counter starts to count with the RC oscillator. It will generate a reset signal when overflows. The WDTE bit will be cleared to 0 automatically when SM79108 been reset, either hardware reset or WDT reset. To reset the WDT is done by setting 1 to the CLEAR bit of WDTC before the counter overflow. This will clear the content of the 16-bit counter and let the counter re-start to count from the beginning.
1.1 Watch Dog Timer Registers: Watch Dog Key Register - (WDTKEY, 97H)
bit-7 WDT KEY7 Read / Write: Reset value: W 0 WDT KEY6 W 0 WDT KEY5 W 0 WDT KEY4 W 0 WDT KEY3 W 0 WDT KEY2 W 0 WDT KEY1 W 0 bit-0 WDT KEY0 W 0
By default, the WDTC is read only. User need to write values 1EH, 0E1H sequentially to the WDTKEY(97H) register to enable the WDTC write attribute, That is MOV WDTKEY, # 1EH MOV WDTKEY, # E1H When WDTC is set, user need to write another values E1H, 1EH sequentially to the WDTKEY(97H) register to disable the WDTC write attribute, That is MOV WDTKEY, # E1H MOV WDTKEY, # 1EH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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January 2003
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SM79108
Watch Dog Timer Registers - WDT Control Register (WDTC, 9FH)
bit-7 WDTE Read / Write: Reset value: R/W 0 R 0 CLEAR R/W 0 Unused * Unused * PS2 R/W 0 PS1 R/W 0 bit-0 PS0 R/W 0
WDTE : Watch Dog Timer enable bit CLEAR : Watch Dog Timer reset bit PS[2:0] : Overflow period select bits PS [2:0] 000 001 010 011 100 101 110 111 Overflow Period (ms) 2.048 4.096 8.192 16.384 32.768 65.536 131.072 262.144
System Control Register (SCONF, 0BFH)
bit-7 WDR Read / Write: Reset value: R/W 0 Unused * Unused * Unused * Unused * Reserved * Unused * bit-0 ALEI R/W 0
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1 ALEI : ALE output inhibit bit, to reduce EMI Setting bit 0 (ALEI) of SCONF can inhibit the clock signal in Fosc/6Hz output to the ALE pin. The bit 7 (WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated by WDT overflow. User should check WDR bit whenever unpredicted reset happened.
2. Reduce EMI Function
The SM79108 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This function will inhibit the clock signal in Fosc/6Hz output to the ALE pin.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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January 2003 3. Port 4 for PLCC or QFP package:
Preliminary
SM79108
The bit addressable port 4 is available with PLCC or QFP package. The port 4 has only 4 pins and its port address is located at 0D8H. The function of port 4 is the same as the function of port 1, port 2 and port 3.
Port4 (P4, 0D8H)
bit-7 Unused Read / Write: Reset value: * Unused * Unused * Unused * P4.3 R/W 1 P4.2 R/W 1 P4.1 R/W 1 bit-0 P4.0 R/W 1
The bit 3, bit 2, bit 1, bit 0 output the setting to pin P4.3, P4.2, P4.1, P4.0 respectively.
4. SPWM Function Description:
The 8-bit SPWM channel is composed of an 8-bit register which contains a 5-bit SPWM in MSB portion and a 3-bit binary rate multiplier (BRM) in LSB portion. The value programmed in the 5-bit SPWM portion will determine the pulse length of the output. The 3-bit BRM portion will generate and insert certain narrow pulses among an 8-SPWM-cycle frame. The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. The usage of the BRM is to generate equivalent 8-bit resolution SPWM type DAC with reasonably high repetition rate through 5-bit SPWM clock speed. The SPFS[1:0] settings of SPWMC (0A3H) register are divided of Fosc to be SPWM clock, Fosc/ 2^(SPFS[1:0]+1). The SPWM output cycle frame repetition rate (frequency) equals (SPWM clock)/32 which is [Fosc/ 2^(SPFS[1:0]+1)]/32.
4.1 SPWM Registers - P1CON, SPWMC0, SPWMD0 SPWM Registers - Port1 Configuration Register (P1CON, 9BH)
bit-7 Unused Read / Write: Reset value: * Unused * PWME0 R/W 0 Unused * Unused * SPWME0 R/W 0 Unused * bit-0 Unused *
SPWME0 : When the bit set to one, the corresponding SPWM pin is active as SPWM function. When the bit reset to zero, the corresponding SPWM pin is active as I/O pin. Four bits are cleared upon reset. PWME0 : When the bit set to one, the corresponding PWM pin is active as PWM function. When the bit reset to zero, the corresponding PWM pin is active as I/O pin. Four bits are cleared upon reset.
SPWM Registers - SPWM Control Register (SPWMC, 0A3H)
bit-7 Unused Read / Write: Reset value: * Unused * Unused * Unused * Unused * Unused * SPFS1 R/W 0 bit-0 SPFS0 R/W 0
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SPFS[1:0]: These two bits is 2's power parameter to form a frequency divider for input clock. SPFS1 0 0 1 1 SPFS0 0 1 0 1 Divider 2 4 8 16 SPWM clock, Fosc=20MHz 10MHz 5MHz 2.5MHz 1.25MHz SPWM clock, Fosc=24MHz 12MHz 6MHz 3MHz 1.5MHz
SPWM Registers - SPWM Data Register (SPWMD0, 0A4H)
bit-7 SPWMD04 Read/Write: Reset value: R/W 0 SPWMD03 R/W 0 SPWMD02 R/W 0 SPWMD01 R/W 0 SPWMD00 R/W 0 BRM02 R/W 0 BRM01 R/W 0 bit-0 BRM00 R/W 0
SPWMD0[4:0]: content of SPWM Data Register. It determines duty cycle of SPWM output waveform. BRM[2:0]: will insert certain narrow pulses among an 8-SPWM-cycle frame N = BRM[2:0] 000 001 010 011 100 101 110 111 Number of SPWM cycles inserted in an 8-cycle frame 0 1 2 3 4 5 6 7
Example of SPWM timing diagram:
MOV SPWMD0 , #83H MOV P1CON , #04H ; SPWMD0[4:0]=10h (=16T high, 16T low), BRM0[2:0] = 3 ; Enable P1.2 as SPWM output pin
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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January 2003
1st cycle frame
32T
Preliminary
SM79108
2nd cycle frame 3rd cycle frame
32T 32T
4th cycle frame 5th cycle frame
32T 32T
6th cycle frame 7th cycle frame
32T 32T
8th cycle frame
32T
16T
16T
16T
16T
16T
16T
16T
16T
1T 1T (narrow pulse inserted by BRM0[2:0] setting, here BRM0[2:0]=3)
1T
SPWM clock = 1 / T = Fosc / 2^(SPFS[1:0]+1) The SPWM output cycle frame frequency = SPWM clock / 32 = [Fosc/2^(SPFS[1:0]+1)]/32 If user use Fosc=20MHz, SPFS[1:0] of SPWMC=#03H, then SPWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz SPWM output cycle frame frequency = (20MHz/2^4)/32=39.1KHz
5. PWM Function Description:
Each PWM channel contains a 8-bit wide PWM data register (PWMDR) to decide number of continuous pulses within a PWM frame cycle. The value programmed in the register will determine the pulse length of the output. The PWM channel can be configured as 5-bit or 8-bit resolution. If a channel is configured as 5-bit resolution, only LSB 5 bits are available. The value of each PWM Data Register (PWMDR) is continuously compared with the content of an internal counter to determine the state of each PWM channel output pin.
5.1 PWM Registers - PWMC0, PWMD0 PWM Registers - PWM Control Register (PWMC0, 0D3H)
bit-7 Unused Read / Write: Reset value: * Unused * Unused * Unused * Unused * PBS R/W 0 PFS1 R/W 0 bit-0 PFS0 R/W 0
PFS[1:0]: These two bits is 2's power parameter to form a frequency divider for input clock. PBS: This bit decides channel bit resolution. If PBS is set, the channel is 5-bit resolution.
PFS1 PFS0
Divider 16 32 64 128
PWM clock, Fosc=12MHz 750KHz 375KHz 187.5KHz 93.75KHz
PWM clock, Fosc=24MHz 1.5MHz 750KHz 375KHz 187.5KHz
0 0 1 1
0 1 0 1
Example : If user use Fosc = 20MHz, PFS[1:0] of PWMC = #03H, PBS = 0, then PWM Clock = 20MHz / 128 = 156.25KHz PWM Output cycle frame frequency = 156.25KHz / 256 = 610 Hz Note : For bzzer application
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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January 2003
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SM79108
PWM Registers - PWM Data Register (PWMD0, 0B3H)
bit-7 PWMD07 Read /Write: Reset value: R/W 0 PWMD06 R/W 0 PWMD05 R/W 0 PWMD04 R/W 0 PWMD03 R/W 0 PWMD02 R/W 0 PWMD01 R/W 0 bit-0 PWMD00 R/W 0
PWM[7:0]: content of PWM Data Register. If PBS is set, only PWM[4:0] are available.
Example of PWM timing diagram:
For 5-bit resolution channel, M = content of PWMD0: M = 00H
32T
M = 01H
M = 0FH
M = 1FH
For 8-bit resolution channel: M = 00H
256T
M = 01H
M = 7FH
M = 0FFH PWM clock = 1/T = Fosc / 2^ ( PFS [1:0] + 1 )
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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January 2003
Preliminary
SM79108
6. Analog-to-Digital Converter (ADC)
The SM79108 equips with 4-channels, 8-bit ADC which is available at P3.4~P3.7. S/W can select one of the 4 ADC channels by setting SFR ADC Status and Control Register (ADSCR, 8EH) bit CH0~CH1. The ADC can do single conversion or continuously conversion. When the conversion is completed, ADC puts the result in the ADC Data Register (ADCD, 8FH) and sets COM bit of ADSCR (ADSCR.7). After channel selection bit CH[1:0] of ADSCR and P3CON been set, the selected pin of P3.4~P3.7 will function as ADC input pin instead of general purpose I/O pin which is due to priority of ADC function is higher than I/O function. The rest of the P3.4~P3.7 pin will still function as general purpose I/O pin. Writes to the port register will have no affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return the value in the port which is been read.
6.1 Straight line conversion
The ADC conversion relationship of input analog signal to digital output value is a linear straight line conversion relationship. It will convert input signal in +Vdd V or above to 0FFH (full scale) and convert input signal +0V or below to 00H. The +Vdd is the voltage applied to the IC.
6.2 ADC input clock frequency range
ADC input clock frequency range = 500KHz ~ 2.5MHz. User need to be aware of this frequency range limitation when using ADC function. The frequency range limitation was induced by the sample-and-hold and DAC converter circuits inside of the ADC submodule. If the ADC input clock frequency resides outside of the range then ADC function may not work. ADC input clock frequency = oscillator frequency / divider. Divider elected by ADCSS[1:0] setting of ADSCR One conversion time = 20 ADC clock cycles / ADC input clock frequency Maximum sample rate of ADC = ADC input clock frequency / 20
6.3 ADC registers - ADSCR, ADR ADC Registers - ADSCR, 8EH)
bit-7 COM Read /Write: Reset value: R 0 CON R/W 0 ADCSS1 R/W 0 ADCSS0 R/W 0 CH1 R/W 0 CH0 R/W 0 R * bit-0 R *
COM: ADC conversion complete bit. This bit is a read only bit which is set each time conversion is completed. It is cleared whenever ADSCR is written or ADCD is read. Reset clears this bit. COM = 1 means conversion completed COM = 0 means conversion not completed CON: ADC continuous conversion bit. When set, the ADC will convert samples continuously and update the ADCD register at the end of each conversion. When reset, only one conversion is allowed. Reset clears this bit. CON = 1 means continuous mode CON = 0 means signal mode
Specifications subject to change without notice,contact your sales representatives for the most recent information.
12/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003
ADCSS[1:0]: ADCSS channel select bit. ADCSS1 0 0 1 1 ADCSS0 0 1 0 1
Preliminary
SM79108
ADC_CLK Fosc / 8 (below 20MHz) Fosc / 16 Fosc / 32 Fosc / 64
CH[1:0] : ADC channel select bit. These bits are used to select one of the ADC channels. CH1 0 0 1 1 CH0 0 1 0 1 Input select CH0 CH1 CH2 CH3
Note: ADC_CLK frequency range 500KHz ~ 2.5MHz
ADC registers - ADC Data Register (ADCD, 8FH)
bit-7 AD7 Read /Write: Reset value: R 0 AD6 R 0 AD5 R 0 AD4 R 0 AD3 R 0 AD2 R 0 AD1 R 0 bit-0 AD0 R 0
ADC puts the result in the ADC Data Register (ADCD, 8FH) after each conversion. The ADCD register is read only register. The content of the ADCD will be 00H after reset. Ex : Osc = 20MHz ADCSS[1:0] = 00 ADC input clock = 20/8 = 2.5MHz (Max) One conversion time = 20 / 2.5MHz = 8us ADC Max sample reta = 2.5MHz / 20 = 125KHz
Port 3 Configuration Register (P3CON, 9DH)
bit-7 ADCE3 Read /Write: Reset value: Set ADCE3 ADCE3 Set ADCE2 ADCE2 R/W 0 ADCE2 R/W 0 ADCE1 R/W 0 ADCE0 R/W 0 Unused * Unused * Unused * bit-0 Unused *
= 1 enables the ADC function on pin P3.7/A15/ADC3, = 0 disables the ADC function on pin P3.7/A15/ADC3, = 1 enables the ADC function on pin P3.6/A14/ADC2, = 0 disables the ADC function on pin P3.6/A14/ADC2,
Specifications subject to change without notice,contact your sales representatives for the most recent information.
13/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003
Set ADCE1 ADCE1 Set ADCE0 ADCE0
Preliminary
SM79108
= 1 enables the ADC function on pin P3.5/A13/ADC1, = 0 disables the ADC function on pin P3.5/A13/ADC1, = 1 enables the ADC function on pin P3.4/A12/ADC0, = 0 disables the ADC function on pin P3.4/A12/ADC0,
User may compare bits ADCE[3:0] of P3CON with bits CH[1:0] of ADSCR. User may consider P3CON as register for distinguish general purpose I/O function from other specific functions. After bit ADCE[3:0] been set, the corresponding I/O pin will be assigned as high impedance input pins for signal input. On the other hand, the setting of CH[1:0] will select ADC channels accordingly.
6.4 ADC Interrupt
The ADC module will generate one interrupt once one analog-to-digital conversion is completed. The ADC interrupt vector locates at 4BH. There are three SFRs for configuring ADC interrupt: IP1, IE1 and IFR. To use ADC interrupt is the same as to use other generic 8052 interrupts. That means using EADC of IE1 for enable/disable ADC interrupt, using PADC for assign ADC interrupt priority. Whenever ADC interrupt occurs, ADCIF will be set to 1. After ADC interrupt subroutine (vector) been executed, ADCIF will be cleared to 0.
Interrupt Priority I Register (IP1, 0B9H)
bit-7 Unused Read /Write: Reset value: * Unused * Unused * Unused * PADC R/W 0 Unused * Unused * bit-0 Unused *
Interrupt priority bit PADC = 1 assigns high interrupt priority of ADC interrupt Interrupt priority bit PADC = 0 assigns low interrupt priority of ADC interrupt
Interrupt Enable I Register (IE1, 0A9H)
bit-7 Unused Read /Write: Reset value: * Unused * Unused * Unused * EADC R/W 0 Unused * Unused * bit-0 Unused *
Interrupt enable bit EADC = 1 enables the ADC interrupt Interrupt priority bit EADC = 0 disables the ADC interrupt
Interrupt Flag Register (IFR, 0AAH)
bit-7 Unused Read /Write: Reset value: * Unused * Unused * Unused * ADCIF R/W 0 Unused * Unused * bit-0 Unused *
Interrupt flag bit ADCIF will be set to 1 when ADC interrupt occurs. Interrupt flag bit ADCIF will be clear to 0 if ADC Interrupt subroutine executed.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
14/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003 7. LCD Driver
Preliminary
SM79108
SM79108 incorporates an on-chip LCD driver which generates segment and common signals output according to the display data saved in LCD buffer registers (0E1H~0E7H) and incorporates segment and common drivers which can drive the LCD panel directly. The on chip LCD Driver has the following features: 1/4 duty (time multiplexing by 4) and 1/3 bias LCD segment driver 0.88 mA operation current (1.2 uA in power down mode) 56 bits of display data buffer 14 segment driver and 4 common driver outputs A frames frequency can be selected
7.1 LCD Control register (LCDCON, 0DFH)
bit-7 LCD_ON Read /Write: Reset value: R/W 0 LCD_EN R/W 0 SEG R/W 0 Unused * Unused * LS2 R/W 0 LS1 R/W 0 bit-0 LS0 R/W 0
LCDCON7~LCDCON0: LCD control register is used to control LCD driver operation LCD_ON: LCD display bit = 1:LCD display ON = 0:LCD display OFF LCD_EN: LCD enable bit SEG: = 1:enables the LCD function on pin #PSEN/SEG4 and ALE/SEG5 = 0:no operation LS[2:0]: Frequency prescaler select, determine the clock frequency of LCD driver, Fclk_lcd LS2 0 0 0 1 1 1 1 LS1 0 0 1 1 0 0 1 1 LS0 0 1 0 1 0 1 0 1 PRESCALER SELECT 1 2 4 8 16 32 64 128
Specifications subject to change without notice,contact your sales representatives for the most recent information.
15/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003
Preliminary
SM79108
The clock frequency of LCD driver is obtained using the following formula: Fclk_lcd = { [Fosc / 2 ] / 32 x PRESCALER } The frame of LCD driver is determined as follows: Frame = Fclk_lcd / 256 The typical range of Fframe is: 1026HZ ~ 8HZ at 16MHz (Fosc = 8MHz)
7.2 LCD Buffer Registers (LCDB0 ~ LCDB6, 0E1H ~ 0E7H) Addressing Map of the LCD buffer registers is shown as following:
com3 Mnemonic LCDB0 LCDB1 LCDB2 LCDB3 LCDB4 LCDB5 LCDB6 address E1H E2H E3H E4H E5H E6H E7H Bit7 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 com2 Bit6 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 com1 Bit5 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 com0 Bit4 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 com3 Bit3 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 com2 Bit2 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 com1 Bit1 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 com0 Bit0 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13
7.3 Timing chart of LCD driver output The 14 segment drivers and the 4 common drivers are 4-level outputs that switch between Vcc and the V1, V2 and Vss LCD driver voltages levels. The output states are determined by the display data values which stored in the LCD buffer registers (0E1H ~0E7H). The LCD driver's outputs are used to drive a 1/3-bias, 1/4-duty LCD panel. 7.4 The Output Control of Segments and Commons
Port 2 Configuration Register (P2CON) control COM0 ~ COM3 and SEG0 ~ SEG3 output; Port 0 Configuration Register (P0CON) controls SEG6 ~ SEG13 outputs. The bit 5 of LCD Control Register control the SEG4 and SEG5 outputs.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
16/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003 Figure 6.1 Output states determination
Frame period Vcc V1 COM0 V2 VSS Vcc V1 COM1 V2 VSS Vcc V1 COM2 V2 VSS Vcc V1 COM3 V2 VSS Vcc V1 SEG0 V2 VSS Vcc V1 SEG1 V2 VSS Vcc V1 SEG2 V2 VSS Vcc V1 SEG3 V2 VSS
Preliminary
SM79108
COM0 COM1 COM2 COM3 0 0 0 0
All segments are OFF 1 0 0 0
Segments connected to COM0 are ON 0 1 0 0
Segments connected to COM1 are ON 1 1 1 1
All segments are ON
Specifications subject to change without notice,contact your sales representatives for the most recent information.
17/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003 Operating Conditions
Symbol TA TS VCC5 VCC3 Fosc 25 Fosc 40 Description Operating temperature Storage temperature Supply voltage Supply voltage Oscillator Frequency Oscillator Frequency Min. -40 -55 4.5 3 3.0 3.0
Preliminary
SM79108
Typ. 25 25 5.0 3.3 25 40
Max. 85 155 5.5 3.6 25 40
Unit.
oC oC
Remarks Ambient temperature under bias
V V MHz For 5V, 3.3V application MHz For 5V application
DC Characteristics
(TA = -40 oC to 85 oC, Vcc = 5V) Symbol
VIL1 VIL2 VIH1 VIH2 VOL1 VOL2 VOH1 VOH2 IIL ITL ILI R RST C IO I CC
Parameter
Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Logical 0 Input Current Logical Transition Current Input Leakage Current Reset Pulldown Resistor Pin Capacitance Power Supply Current Vdd RES, XTAL1
Valid
port 0,1,2,3,4,#EA port 0,1,2,3,4,#EA RES, XTAL1 port 12,3,4 port 0,2,port 3.0~port 3.3, ALE, #PSEN port 1, 2, 3, ALE, #PSEN port 0 port 1,2,4, port 3.0~port 3.3 port 1,2,4, port 3.0~ port3.3 port 0, #EA
Min.
-0.5 0 2.0
Max.
1.0 0.8 Vcc+0.5 0.4 0.4
Unit
V V V V V V V V V V " " "
Test Conditions
Vcc = 5V
70%Vcc Vcc+0.5
IOL = 1.6mA IOL = 3.2mA IOH = -60uA IOH = -10uA IOH = -800uA IOH = -80uA Vin = 0.45V Vin = 2.0V Vin = 0.45V Vin = 5V Freq=1MHz, Ta=25oC Active mode, 16MHz Idle mode, 16MHz down mode, 16MHz
2.4 90%Vcc 2.4 90%Vcc -50 -650 10 10 18 90 10 20 10 100
uA uA uA uA Kohm pF mA mA uA
Note1: Under steady state (non-transient) conditions, IOL must be externally Limited as follows: Maximum IOL per port pin : 10mA Maximum IOL per 8-bit port : port 0 :26mA port 1,2,3 :15mA Maximum total IOL for all output pins : 71mA If IOL exceeds the condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. Note2 : Minimum VCC for Power-down is 2V.
Specifications subject to change without notice,contact your sales representatives for the most recent information.
18/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003 AC Characteristics
Preliminary
SM79108
(16/25/40MHz, operating conditions; CL for Port 0, ALE and PSEN Outputs=150pF; CL for all Other Output=80pF) Symbol T LHLL T AVLL T LLAX T LLIV T LLPL T PLPH T PLIV T PXIX T PXIZ T AVIV T PLAZ T RLRH T WLWH T RLDV T RHDX T RHDZ T LLDV T AVDV T LLYL T AVYL T QVWH T QVWX T WHQX T RLAZ T YALH T CHCL T CLCX T CLCH T CHCX T, TCLCL Parameter ALE pulse width Address Valid to ALE low Address Hold after ALE low ALE low to Valid Instruction In ALE low to #PSEN low #PSEN pulse width #PSEN low to Valid Instruction In Instruction Hold after #PSEN Instruction Float after #PSEN Address to Valid Instruction In #PSEN low to Address Float #RD pulse width #WR pulse width #RD low to Valid Data In Data Hold after #RD Data Float after #RD ALE low to Valid Data In Address to Valid Data In ALE low to #WR High or #RD low Address Valid to #WR or #RD low Data Valid to #WR High Data Valid to #WR transition Data hold after #WR #RD low to Address Float #WR or #RD high to ALE high clock fall time clock low time clock rise time clock high time clock period Valid Cycle RD/WRT RD/WRT RD/WRT RD RD RD RD RD RD RD RD RD WRT RD RD RD RD RD RD/WRT RD/WRT WRT WRT WRT RD RD/WRT fosc=16MHz Min. Typ. Max 115 43 53 240 53 173 177 0 87 292 10 365 365 302 0 145 590 542 178 197 230 403 38 73 53 Variable fosc Unit Min. Typ. Max 2xT - 10 nS T - 20 nS T - 10 nS 4xT - 10 nS T - 10 nS 3xT - 15 nS 3xT - 10 nS 0 nS T + 25 nS 5xT - 20 nS 10 nS 6xT - 10 nS 6xT - 10 nS 5xT - 10 nS 0 nS 2xT + 20 nS 8xT - 10 nS 9xT - 20 nS 3xT - 10 3xT + 10 nS 4xT - 20 nS 7xT - 35 nS T - 25 nS T + 10 nS 5 nS 72 T -10 T + 10 nS nS nS nS nS 1/fosc nS ICC VCC RST SM79108 (NC) Clock Signal XTAL2 XTAL1 VSS PO EA 8 Vcc Remarks
63
ICC Active mode test circuit
Vcc
Specifications subject to change without notice,contact your sales representatives for the most recent information.
19/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003
Preliminary
SM79108
Timing Critical, Requirement of External Clock (Vss=0.0V is assumed)
TCLCL
Vdd-0.5V
70%Vdd
0.45V
20%Vdd-0.1V TCHCL TCLCX TCLCH TCHCX
Tm.I External Program Memory Read Cycle
TPLPH
#PSEN ALE PORT 0
TLHLL TAVLL A0 - A7 TAVIV TLLPL TLLAX TPLAZ TPLIV TPXIZ TPXIX Instruction. IN A0 - A7
PORT 2
A8 - A15
A8 - A15
Tm.II
External Data Memory Read Cycle
#PSEN
TYHLH
ALE
TLLDV TLLYL TRLRH
#RD
TAVLL
TLLAX A0 - A7 from Ri or DPL TAVYL TAVDV
TRLDV TRLAZ
TRHDZ TRHDX DATA IN A0 - A7 from PCL INSTRL IN
PORT 0
PORT 2
P2.0 - P2.7 or A8 - A15 from DPH
A8 - A15 from PCH
Specifications subject to change without notice,contact your sales representatives for the most recent information.
20/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003 Tm.III External Data Memory Write Cycle
#PSEN
TLHLL
Preliminary
SM79108
TYHLH
ALE
TLLYL TWLWH
#WR
TAVLL TLLAX
TQVWX
TQVWH
TWHQX
PORT 0
A0-A7 from Ri or DPL
DATA OUT
A0-A7 From PCL
INSTRL IN
TAVYL
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Application Reference
Valid for SM79108 X'tal C1 C2 R X'tal C1 C2 R 3MHz 30pF 30pF open 20MHz 22pF 22pF open 6MHz 30pF 30pF open 25MHz 15pF 15pF 62K 12MHz 30pF 30pF open 33MHz 5pF 5pF 6.8K
XI
16MHz 30pF 30pF open 40MHz 2pF 2pF 4.7K
NOTE: Oscillation circuit may differs with different crystal or ceramic resonator in higher oscillation frequency which was due to each crystal or ceramic resonator has its own characteristics. User should check with the crystal or ceramic resonator manufacturer for appropriate value of external components.
C1 R
X'tal
SM79108
X2 C2
Specifications subject to change without notice,contact your sales representatives for the most recent information.
21/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003
Preliminary
SM79108
40L 600mil PDIP Information
E S D E1
A1
A2 A
C
L e1 B1 B
eA a
Note: 1. Dimension D Max & include mold flash or tie bar burrs. 2. Dimension E1 does not include inter lead flash. 3. Dimension D & E1 include mold mismatch and are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/ intrusion. 5. Controlling dimension is inch. 6. General appearance spec. should base on final visual inspection spec.
Symbol A A1 A2 B B1 C D E E1 e1 L a eA S
Dimension in inch minimal/maximal - / 0.210 0.010 / 0.150 / 0.160 0.016 / 0.022 0.048 / 0.054 0.008 / 0.014 - / 2.070 0.590 / 0.610 0.540 / 0.552 0.090 / 0.110 0.120 / 0.140 0 / 15 0.630 / 0.670 - / 0.090
Dimension in mm minimal/maximal - / 5.33 0.25 / 3.81 / 4.06 0.41 / 0.56 1.22 / 1.37 0.20 / 0.36 - / 52.58 14.99 / 15.49 13.72 / 14.02 2.29 / 2.79 3.05 / 3.56 0 / 15 16.00 / 17.02 - / 2.29
Specifications subject to change without notice,contact your sales representatives for the most recent information.
22/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003 44L Plastic Chip Carrier (PLCC)
6 7
Preliminary
SM79108
L
E
HE y
GE
D HD A2 A C A1
b1 e GD
b
Note: 1. Dimension D & E does not include inter lead flash. 2. Dimension b1 does not include dambar protrusion/ intrusion. 3. Controlling dimension: Inch 4. General appearance spec. should base on final visual inspection spec.
Symbol A A1 A2 b1 b C D E e GD GE HD HE L
y
Dimension in inch minimal/maximal - / 0.185 0.020 / 0.145 / 0.155 0.026 / 0.032 0.016 / 0.022 0.008 / 0.014 0.648 / 0.658 0.648 / 0.658 0.050 BSC 0.590 / 0.630 0.590 / 0.630 0.680 / 0.700 0.680 / 0.700 0.090 / 0.110 - / 0.004 /
Dimension in mm minimal/maximal - / 4.70 0.51 / 3.68 / 3.94 0.66 / 0.81 0.41 / 0.56 0.20 / 0.36 16.46 / 16.71 16.46 / 16.71 1.27 BSC 14.99 / 16.00 14.99 / 16.00 17.27 / 17.78 17.27 / 17.78 2.29 / 2.79 - / 0.10 /
Specifications subject to change without notice,contact your sales representatives for the most recent information.
23/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003
Preliminary
SM79108
44L Plastic Quad Flat Package
C L S e L1 2 R1 D2 D1 D b A2 3 R2 A1 Gage Plane 0.25 mm
E2 E1 E e1 A
seating plane e
C
Note: Dimension D1 and E1 do not include mold protrusion. Allowance protrusion is 0.25mm per side. Dimension D1 and E1 do include mold mismatch and are determined datum plane. Dimension b does not include dumber protrusion. Allowance dumber protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dumber cannot be located on the lower radius or the lead foot.
Symbol A A1 A2 b c D D1 D2 E E1 E2 e L L1 R1 R2 S 1 2 3 C
Dimension in Inch minimal/maximal - / 0.100 0.006 / 0.014 0.071 / 0.087 0.012 / 0.018 0.004 / 0.009 0.520 BSC 0.394 BSC 0.315 0.520 BSC 0.394 BSC 0.315 0.031 BSC 0.029 / 0.041 0.063 0.005 / 0.005 / 0.012 0.008 / 0 / 7 0 / 10 REF 7 REF 0.004
Dimension in mm minimal/maximal - / 2.55 0.15 / 0.35 1.80 / 2.20 0.30 / 0.45 0.09 / 0.20 13.20 BSC 10.00 BSC 8.00 13.20 BSC 10.00 BSC 8.00 0.80 BSC 0.73 / 1.03 1.60 0.13 / 0.13 / 0.30 0.20 / as left as left as left as left 0.10
Specifications subject to change without notice,contact your sales representatives for the most recent information.
24/26
Preliminary
Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003
Preliminary
SM79108
eMCU Writer List
Company Advantech 7F, No.98, Ming-Chung Rd., Shin-Tien City, Taipei, Taiwan, ROC Web site: http://www.aec.com.tw Hi-Lo 4F, No. 20, 22, LN, 76, Rui Guang Rd., Nei Hu, Taipei, Taiwan, ROC. Web site: http://www.hilosystems.com.tw Leap 6th F1-4, Lane 609, Chunghsin Rd., Sec. 5, Sanchung, Taipei Hsien, Taiwan, ROC Web site: http://www.leap.com.tw Xeltek Electronic Co., Ltd 338 Hongwu Road, Nanjing, China 210002 Web site: http://www.xeltek-cn.com Contact info Tel:02-22182325 Fax:02-22182435 E-mail: aecwebmaster@advantech.com.tw Programmer Model Number LabTool - 48 (1 * 1) LabTool - 848 (1*8) * Note: Not yet, about 3/E'03
Tel:02-87923301 Fax:02-87923285 E-mail: support@hilosystems.com.tw
All - 11 (1*1) Gang - 08 (1*8) * Note: Not yet, about 3/E'03
Tel:02-29991860 Fax:02-29990015 E-mail: service@leap.com.tw
SU - 2000 (1*8) * Note: Not yet, about 3/E'03
Tel:+86-25-4408399, 4543153-206 E-mail: xelclw@jlonline.com, xelgbw@jlonline.com
Superpro/2000 (1*1) Superpro/680 (1*1) Superpro/280 (1*1) Superpro/L+(1*1) * Note: Not yet, about 3/E'03
Specifications subject to change without notice,contact your sales representatives for the most recent information.
25/26
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Ver 1.0
SM79108 01/03
SyncMOS Technologies Inc.
January 2003 Feedback / Inquiry: To Attn Fax Tel :SyncMOS Technologies, Inc. :MKT / Customer Service Dept. :886-3-579-2960 :886-3-578-0493 :886-3-579-2987 :886-3-578-3344 # 2667
Preliminary
SM79108
From
:
Company : Dept, Section : Position Title : Inquiry Date : Ref No :
Description:
Specifications subject to change without notice,contact your sales representatives for the most recent information.
26/26
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SM79108 01/03

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